Automatic synthesis of reactive agents

Abstract

This paper introduces a new approach to designing smart control chips that enables automatic synthesis of real-time control systems from agent specifications. An agent specification is compiled into a hardware description format, such as RTL-VHDL (Register Transfer Level-VLSI Hardware Description Language) or RTL Verilog, which is synthesized using computer-assisted tools to develop ASIC masks or FPGA configurations. A rule-based specification language called Layered Argumentation System (LAS) is defined and a sound and complete mapping to Verilog is developed. LAS combines fuzzy reasoning and nonmonotonic reasoning. This enables chip designers to capture commonsense knowledge and concepts having varying degrees of confidence collaboratively and incrementally.